1. Field of the Invention
The present invention generally relates to a level converter which converts an input voltage level into another level, and more particularly to a level converter which is suitably provided in an LSI device and boosts the voltage of a signal, a boosted signal being output to the outside of the LSI device.
Recent LSI devices (semiconductor devices) are required to have a low power consumption and a low noise characteristic. Nowadays, the LSI devices are designed to operate with a reduced internal power supply voltage in order to satisfy the above requirement.
2. Description of the Related Art
A reduced internal power supply voltage is applied to an internal circuit of an LSI device in order to attempt to reduce the power consumed therein and operate at a low noise level. When such an LSI device is used, it is required to consider the conformity with a power supply voltage applied to an external circuit or device connected to the LSI device. Hereinafter, such an external circuit or device will be referred to as external interface circuit.
If the internal power supply voltage applied to the internal circuit of the LSI device is lower than the power supply voltage applied to the external interface circuit and is applied thereto without any modification, the external interface circuit will not operate normally. For example, if the internal power supply voltage is 3 V and the power supply voltage applied to the external interface circuit is 5 V, the signal output by the internal circuit of the LSI device swings between 0 V and 3 V (an amplitude equal to 3 V). The external interface circuit requires a signal input which swings between 0 V and 5 V (an amplitude equal to 5 V). Hence, a level converter is provided inside the LSI device and converts the voltage of the signal to a level necessary for the external interface circuit to operate properly. In the example as described above, the level converter converts the 3V signal output by the internal circuit of the LSI device into a 5V signal, which is then output to the external interface circuit.
FIG. 1 is a circuit diagram of a conventional level converter, which is made up of field-effect transistors M3, M4, M5 and M6 connected in a fashion shown therein. The transistors M3-M6 are, for example, MOS (Metal Oxide Semiconductor) transistors. The transistors M3 and M5 are P-channel MOS transistors, and the transistors M4 and M6 are N-channel MOS transistors. A power supply connected to the level converter has a high potential VDD2, and is equal to the high potential of a power supply supplied to an external interface circuit provided outside of the LSI device equipped with the above level converter and connected thereto. The power supply connected to the level converter has a low potential GND, which is the ground level. Hereinafter, the power supply voltage includes the meaning of the high potential of the power supply.
The transistors M1 and M2 are components of an internal circuit of the LSI device. The internal circuit is formed together with other components (not shown). The transistors M1 and M2 operate with an internal power supply having a high potential VDD1. The internal power supply voltage VDD1 is lower than the external power supply voltage VDD2 (VDD1&lt;VDD2). The transistors M1 and M2 form an inverter (CMOS inverter).
A signal IN is supplied to the transistors M1 and M2 from a previous-stage circuit (not shown), which is a part of the internal circuit. The signal IN is applied to the gates of the transistors M1, M2 and M6. An output signal OUT of the level converter is obtained at a node at which the drains of the transistors M5 and M6 are connected together.
When the signal IN is at a low level, the transistors M1 and M4 are ON, and the gate of the transistor M5 is at the ground level GND. At this time, the transistor M6 is OFF. Hence, the output signal OUT is at a high level equal to the power supply voltage VDD2. When the signal IN is at a high level, the transistor M6 is ON, and the output signal OUT is at a low level equal to the ground level GND. At this time, the inverter outputs the low-level signal, and thus the transistor M4 is OFF. Since the transistor M6 is ON, the transistor M3 is ON.
In practice, as shown in FIG. 2, a buffer circuit 10 is provided so as to follow the level converter. An output terminal of the buffer circuit is connected to a terminal 11 for use in an external connection. The buffer circuit 10 is made up of a P-channel field-effect transistor M7 and an N-channel field-effect transistor M8. The output signal of the level converter is applied to the gates of the transistors M7 and M8.
In practice, there is a case as shown in FIG. 3. A circuit 12 having the same configuration as that made up of transistors M1-M6 is provided. The circuit 12 receives an input signal IN2 and has an output terminal connected to the gate of the transistor M8. An input signal IN1 is applied to the gates of the transistors M1 and M2 shown in FIG. 3. The input signal IN2 can be different from or identical to the input signal IN1. The circuit configuration shown in FIG. 3 is different from that shown in FIG. 2 in that the circuit configuration shown in FIG. 3 can set the terminal 11 to a high-impedance state. More particularly, when both the transistors M7 and M8 are turned OFF, the terminal 11 can be set to the high-impedance state.
However, the above-mentioned level converter has a disadvantage in that a pass-through current flows as indicated by broken lines shown in FIGS. 2 and 3 and thus a large amount of energy is consumed in the buffer circuit 10.
The internal power supply voltage VDD1 can be derived, in the LSI device, from the power supply voltage VDD2 externally supplied, or can be externally supplied. In any case, nodes N2 and N3 have indefinite voltages, as indicated in FIGS. 2 and 3, due to the relationship between the power supply voltages VDD1 and VDD2. As shown in FIG. 4, if the power supply voltage VDD2 rises first and the internal power supply voltage VDD1 rises second, the above problem will occur. More particularly, when the power supply voltage VDD2 rises while the internal power supply voltage VDD1 is equal to 0 V, the gate voltages of the transistors M1 and M2 (in other words, the signals IN (or IN1 and IN2)) are 0 V and the voltage of the node N1 is also 0 V. Hence, the transistors M4 and M6 are in the OFF state, and thus the nodes N2 and N3 are in the indefinite state. The indefinite voltages of the nodes N2 and N3 in the indefinite state may fall within a range shown as a hatched area in FIG. 4. If the indefinite voltage is applied to the node N3, both the transistors M7 and M8 will be turned ON, and the pass-through current will flow as shown in FIG. 2 or FIG. 3.
The above pass-through current will flow when the power supply is turned ON in the configuration in which the internal power supply voltage VDD1 is produced from the external power supply voltage VDD2. The pass-through current will also flow when both the voltages VDD1 and VDD2 are supplied externally and the voltage VDD1 is equal to or approximately equal to 0 V due to a fault or a particular factor which requires the power supply voltage VDD1 to be set equal to 0 V. In practice, many circuits like the configuration shown in FIG. 2 or FIG. 3 are formed in the LSI device, and the pass-through currents flow in the respective circuits. Hence, a large amount of current flows in total, and a large amount of energy is consumed in the LSI device.
As described above, the output voltage OUT of the conventional level converter can be settled (fixed) only when both the power supply voltages VDD1 and VDD2 are certainly applied to the circuit including the level converter. If the internal power supply voltage VDD1 is equal to or approximately equal to 0 V, the pass-through current will flow.